The present invention relates to sampling circuits, and more particularly to a high speed track and hold with dual pump circuit that may be used in a sampling circuit to achieve requisite high speed and accuracy.
Many electronic functions employ sampling circuits for sampling an input signal. The present disclosure, for example, describes an analog to digital converter (ADC) that employs a sample circuit including at least one track and hold circuit to aid in comparison and digital conversion. It is noted that the present invention is not limited to ADC applications but may be applied to any application in which sampling circuits are employed and in which it is desired to maintain a requisite accuracy level. The desired level of linearity, accuracy and resolution of the particular ADC described herein is relatively high and requires 14-bit resolution of the output digital values. In this manner, it is desired that the track and hold circuit(s) used to sample an input signal maintain better than 14-bit accuracy.
The ADC is intended to be incorporated into a monolithic unit on one substrate of an integrated circuit (IC) or chip. The overall passive component match for most silicon processes is 0.1% in accuracy. This translates into overall accuracy of approximately 10 bits. Only a slight improvement is possible by careful optimization and use of dummy components in the layout of the passives. Sometimes, statistical matching using arrays of passives can yield up to an order of magnitude improvement in the overall accuracy.
Correction and calibration techniques are known to improve the resolution, such as laser trimming or fuse blowing. Such post-processing techniques, however, must be performed on a part-by-part basis thereby unduly complicating and increasing cost of the manufacturing process. Also, such post-processing techniques operate under fixed conditions and do not correct for inaccuracies or changes due to temperature, aging and/or operating conditions. Integrated calibration techniques are also known and usually operate to measure error at the backend and apply a correction factor. Such calibration techniques are limited by quantization and usually limit correction to one-half bit of resolution of the converter itself. Also, the calibration techniques are incorporated in silicon and thus subject to the same limitations of the target circuitry.
It is desired to provide a track and hold circuit that operates at relatively high speed while maintaining a relatively high level of accuracy. It is desired to meet these goals without being limited by accuracy limitations of the fabrication process and without interfering with or overly complicating the manufacturing process.
A dual pump circuit according to an embodiment of the present invention includes a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, where each transistor has a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor.
In one configuration, the p-channel transistor is a PMOS transistor and the first pump circuit is a PMOS charge pump circuit coupled to drive the gate of the PMOS transistor. Also, the n-channel transistor is an NMOS transistor and the second pump circuit is an NMOS charge pump circuit coupled to drive the gate of the NMOS transistor. The first and second pump circuits are each operative to maintain gate to source voltage minus the threshold voltage of a corresponding transmission gate transistor constant for a varying signal at the dual pump input. In one embodiment, the PMOS and NMOS transistors are approximately equal in size. In another embodiment, the PMOS and NMOS transistors each have approximately the same conductance.
A specific embodiment of the first and second pump circuits includes a source follower and a switched capacitor circuit. The source follower is coupled to the dual pump input and the switched capacitor circuit is coupled to the source follower circuit and to the control terminal of the corresponding transmission gate transistor. The switched capacitor circuit combines input voltage with a change in threshold voltage and controls the control terminal of the corresponding transmission gate transistor based on the combined voltage. The source follower circuit may include an operational amplifier coupled to the dual pump input, a MOS transistor having a control terminal coupled to an output of the differential amplifier and a pair of current terminals coupled between a supply voltage and an inverting input of the differential amplifier, and a constant current bias coupled to the inverting input of the differential amplifier. In this latter case, a gamma parameter of the MOS transistor and a corresponding one of the transmission gate transistors may be made approximately equal to provide threshold voltage compensation.
A track and hold circuit for sampling an input signal according to an embodiment of the present invention includes at least one dual pump sampling circuit, at least one sampling capacitor, and a sample control circuit. Each dual pump sampling circuit includes a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, where each transistor has a control terminal and a pair of current terminals coupled between the input signal and a sampling capacitor. The dual charge pump includes first and second pump circuits, where each has an input coupled to receive the input signal, an output coupled to a control terminal of a corresponding one of the p-channel and n-channel transistors, and an activation input. Each dual charge pump is configured to linearize operation of a corresponding one of the transmission gate transistors. The sample control circuit is coupled to activation inputs of each of the at least one dual pump sampling circuit and to each sampling capacitor. The sample control circuit is operative to activate the dual pump sampling circuit to sample the input signal via the at least one sampling capacitor, and then to deactivate each dual pump sampling circuit to provide a sampled output signal.